Resources

Title

Introduction to SDH

Overview

The Synchronous Digital Hierarchy forms the backbone infrastructure of the world’s telecom networks. This presentation presents the evolution of the SDH network, covering topics such as advantages over PDH, multiplex structure, synchronisation, transport of asynchronous payloads, types of payloads and so on. This is a useful guide for those that need an introduction to the topic, and a skeleton framework for further research into the standards.

Download

Introduction to SDH (PDF 163KB)

Title

Linux Clusters: A Brief Introduction to Linux and Linux Clusters

Abstract

This presentation provides a brief explantaion into the history, development and functionality of Linux clusters. Cluster structures are compared and contrasted against each other and existing supercomputer designs.

Download

A brief Introduction to Linux and Linux Clusters (PDF 197 K

Title

Proactively Managing Voice Quality on VoIP Networks

Abstract

Voice over IP (VoIP) is delivering savings to businesses, call centres and carriers, but what do the users think about it? This paper outlines the issues concerned with the quality of voice, both from an historical perspective and as it applies to VoIP. Common phenomena are discussed and frequent faults and their causes are detailed. The reasons for proactively managing VoIP voice quality are examined as are the means of doing so.

Download

Proactively Managing Voice Quality on VoIP Networks (PDF 838KB)

Title

Voice Quality Monitoring for VoIP Networks

Abstract

This paper describes the voice quality issues faced by VoIP service providers, and how they can proactively manage voice quality within their network. Results are presented showing how the deployment of non-intrusive voice quality monitoring equipment enables critical early warning when there is a network problem, and allows service providers to pin-point and eliminate the causes of voice quality degradation. It also enables evaluation of the performance of voice quality enhancement equipment within the network.

Download

Voice Quality Monitoring for VoIP Networks (PDF 242KB)

Voice Quality Monitoring for VoIP Networks Japanese Translation (PDF 353KB)

Title

Network Processors - Evaluating Architectures for Leading Edge Applications

Abstract

The need for higher layer processing in network equipment to implement flexible devices such as Load Balancers, Web Switches and deep packet processing for security applications has led to the creation of the Network Processor.  These must be capable of processing packet data at wire-speed, which creates new challenges not previously seen in processor design.  Many varied and innovative approaches have been taken to overcome these obstacles.

This whitepaper firstly discusses the applications for Network Processors, elaborating this into some fundamental requirements of such devices.  Secondly, the trade-offs in Network Processor design are discussed.  Finally, a number of architectural approaches are described in the context of how well they perform in packet processing applications and the limitations each have.  The implications on the adopted programming model are also discussed.

Download

Network Processors - Evaluating Architectures (PDF 2,973KB)

Title

Signal Integrity Considerations for High Speed Digital Hardware Design

Abstract

As system clock frequencies and rise times increase, signal integrity design considerations are becoming ever more important.  Unfortunately many Digital Designers may not recognise the importance of signal integrity issues and problems may not be identified until it is too late.

This paper presents the most common design issues affecting signal integrity in high-speed digital hardware design.  These include impedance control, terminations, ground/power planes, signal routing and crosstalk.  Armed with the knowledge presented here, a digital designer will be able to recognise potential signal integrity problems at the earliest design stage.  Also, the designer will be able to apply techniques presented in this paper to prevent these issues affecting the performance of their design.

Download

Signal Integrity Considerations for High Speed Digital Hardware (PDF 1,582KB)

Title

Strategies for ASIC Board Level Validation

Abstract

With the advent of multi-million gate System-On-a-Chip (SOC) ASIC devices, the validation effort required has become a significant challenge, and can amount to more person-months of effort than the development of the devices themselves.

This paper describes strategies for ASIC board-level validation. It presents the advantages of undertaking an open systems approach to the development of validation strategies, and highlights the opportunities that exist to maximize circuit and embedded software reuse from the validation effort for eventual deployment in the ASIC device end-user context.

A number of validation board architectures are presented, along with a discussion of how these architectures can be extended into a validation system to facilitate chipset testing.

Download

Strategies for ASIC Board-Level Validation (PDF 478KB)