Client Area

Examples of the innovative solutions delivered by the Calyptech team are shown below. References from our clients may be obtained on request. Calyptech withhold our client details from general dissemination; Calyptech have a firm commitment to client confidentiality, and do not disclose our client details without express permission.

• Multi-rate OC-3/OC-12/OC-48 Intellectual Property Core
• Voice Quality Enhancement System E1/T1 Interface
• 40 Gbit/sec Packet Over SONET Protocol Tester
• Network Processor Based 10G Protocol Analysis System
• TDM timeswitch Intellectual Property Core
• xDSL DSP Algorithm Analysis and Performance Modelling
• 40 Gbits/sec Telecommunications System Design
• 10 Gbits/sec ASIC chipset validation environment
• Network Processor based 3G Load Test Card
• 10 Gbits/sec High Speed Router Test System
• FSAN (G.983) ATM PON Chipset

Voice Quality Enhancement System E1/T1 Interface

Lead Customer:
Telstra Australia

Brief:

Telstra had a requirement for a Customised Product Solution to address the Voice Quality issues in their CDMA Wireless Local Loop Deployment in Australia

Key Aspects of Development:

• Assessment of the business case. Calyptech fully funded development after conducting an analysis of the competitive environment, customer requirements, market potential of the solution to be more widely applicable in similar wireless and voice over IP networks worldwide, and alignment with company vision and mission
• Technology evaluation, and identification of technology partnerships
• Requirements Capture, Detailed Design and Implementation
• Early evaluation system deployment to prove the concept and refine algorithms for voice quality enhancement in the presence of non-linear echo paths
• Development of Board level designs, Chip level designs, and embedded real-time software
• Development of scalable architecture, using Calyptech developed backplane interface Intellectual Property
• Safety and EMC Compliance
• Management of Pilot Deployment and Support
• Full Product Development
• Debug of field issues, including interoperability issues with third party equipment
• Development of advanced Element Management system - VQEST-EM

End-Result:

The VQEST 300 Voice Quality Enhancement System was developed and chosen by Telstra for Voice Quality Enhancement in their CDMA Wireless Local Loop network. The decision followed an independent technology evaluation, and successful pilot trial in their live network.

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Network Processor based 10G Protocol Analysis System

Client:
Network security and protocol monitoring equipment manufacturer

Brief:
Investigate the feasibility of using advanced Network Processor based hardware to implement an advanced security and protocol analysis engine, for realisation in a modular platform, with capability at 40Gbits/sec if possible.

Key Aspects of Development:

• Analyse requirements, including use case analysis
• Technology evaluation and comparative analyses for Network Processor devices in the market
• Development of a flexible modular architecture based on off the shelf readily available platforms
• Develop full rate analysis capability at 10Gbits/sec, for packet sizes of 40 bytes or greater
• Development of 10Gbits/sec line card architecture and design

Deliverables:

• Highly configurable architecture, with a recommended Network Processor
• Tailored Backplane to carry aggregate bandwith of 80Gbits/sec
• Backplane simulations including connector modelling to cater for 3.2Gbit/sec highways
• System facilitated legacy client modules
• Solution was scalable to 40Gbit/sec

End-Result:

• Project was cancelled in the early Design Execution phase due to adverse market conditions in 2002
• 10G Line Card, 80Gbit/sec Backplane, Network Processor Protocol engine were designed

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TDM Timeswitch Intellectual Property Core

Client:
Multiple semiconductor and Access Multiplexer system development companies

Brief:
Several Calyptech clients expressed a requirement for a TDM Timeswitch capability that leveraged the facilities in advanced FPGA device technologies, to deliver a tailored switch solution for various applications

Key Aspects of Development:

• Analyse requirements from a set of lead customers
• Identify suitable FPGA technology target
• Integrate flexible interface structure for back and front end interfaces
• Integrate non-blocking function for PMC slot access in cPCI systems
• Develop flexible H.110 interface to allow for timing and rate variances

Deliverables / End-Result:

• Highly configurable TDM Timeswitch IP Core, proven in lead customer hardware target
• Cost effective and integratable alternative to off-the-shelf ASSP devices

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xDSL DSP Algorithm Analysis and Performance Modelling

Client:
Leading North American Based Telecommunications Chip Manufacturer

Brief:

Calyptech were engaged to perform xDSL system analysis and performance modelling, algorithm development and embedded software development.

Key Aspects of Development:

• Analysis of DSP algorithms within client's xDSL chipset

Development of:

• xDSL system performance analysis software;
• timing recovery algorithm for improved modem synchronisation; and
• embedded software development for multi-port xDSL chipset

End-Result:

Calyptech successfully delivered a comprehensive xDSL system analysis report, xDSL performance analysis simulation software, Embedded software for multi-port xDSL chipset and a modem  synchronisation test report.

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40Gbits/sec Telecommunications System Design

Client:
Leading North American Based Telecommunications Systems Company

Brief:
Architect and Design a 40Gbit/sec Telecommunications system, capable of catering for 2.4G, 10G and 40G line cards, with flexible modular architecture.

Key Aspects of Development:

• Multi-site collaboration across two divisions of the client company
• Development of an OC-192 line card
• Development of driver software
• Development of Backplane Interconnectivity Scheme allowing modular solution deployment

Deliverables / End-Result:

• 10G Line Card
• High Speed Backplane with 80Gbits/sec throughput
• High Speed (>200Mhz) FPGA Designs
• Backplane Protocol for data transfer between modules
• Feasibility analyses for alternate technologies for Backplane development

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10Gbits/sec ASIC chipset validation environment

Client:
Leading North American Based Telecommunications Chip Manufacturer

Brief:
Architect and Design a 4-port OC-48 to UL4/PL4 test system to run at 200 MHz using latest Virtex-II devices

Key Aspects of Development:

• Multi-site collaboration across two divisions of the client company
• Development of a test system architecture to address ASIC chipset test requirements
• Development of two Virtex-II devices to bridge the OC-48 to PL4 function using VHDL and Verilog
• Development of an OC-48 line card and 4-port Bridge card mounted in a PCI Chassis, including PCB layout.
• Development of driver software (VxWorks)

Deliverables / End-Result:

• Xilinx Virtex-II 200MHz bridge designs
• Bridge Unit
• OC-48 Line card

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Network Processor based 3G Load Test Card

Client:
Leading North American Based Telecommunications Test Equipment Manufacturer

Brief:
Design a 3G load test card for the client's 3G test system based on the Intel IXP-1200 network processor. This device was connected to a SONET/SDH 155/622Mb/sec optical front-end, with an FPGA used to interface between the network processor and SONET/SDH framer.

Key Aspects of Development:

• Development of PCB incorporating the network processor, associated SDRAM and SSRAM, ethernet interface, FPGA and optical front-end

Deliverables / End-Result:

• Complete 3G load test card PCB
• PCB was successful on first turn, and the project team managed to use the network processor to generate full line-rate traffic within 2 months of the board being powered up for the first time.

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10 Gbits/sec High Speed Router Test System

Client:
Leading North American Based Telecommunications Test Equipment Manufacturer

Brief:
Architect and Design Transmit Path for 10Gbits/sec Packet over Sonet Tester.

Leverage an existing Layer 2 tester PCB to add Layer 3 capability.

Key Aspects of Development:

• Multi-site collaboration across two divisions of the client company.
• Co-development of Virtex-E devices for Transmit Path as part of client team
• Testbench development for Transmit device testing
• Schematic design and PCB layout

Deliverables / End-Result:

• Xilinx Virtex-E designs
• Commission device on Test System board

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FSAN (G.983) ATM PON Chipset

Client:
Leading Japanese Telecommunications Systems Manufacturer

Brief:
Design ATM PON Chipset for asymmetric 622/155 data rates.

Key Aspects of Development:

• Multi-site collaboration across two divisions of the client company.
• Co-development of ASIC
• Testbench development for ASIC
• Validation hardware system
• Driver development for Validation System

Deliverables / End-Result:

• ATM PON ASIC
• Validation Hardware System
• Validation System Driver Development

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