Sonet/SDH

Interface Configuration

Features

• Data rates up to 9.953Gb/s
• OC-192, OC-48, OC-12, GbE, & FC
• CPU Interface
• Suitable for FPGA/ASIC technology

• SONET/SDH Processing
• Loss of Signal Status
• Frame Alignment Status
• B1 Error Count
• B2 Error Count
• AIS Status
• RDI Status
• REI Status
• M1 Octet Capture
• K1/K2 Octet Capture
• J0 Octet Capture

• 8B/10B Processing
• Loss of Signal Status
• Loss of Sync. Count & Status
• Invalid Code Count & Status
• Disparity Error Count & Status

Target Applications

• Performance Monitoring
• Network Analyser

General Description

The 10G Multi-Rate PM core provides multi rate performance monitoring for several standard protocols including SONET, SDH, Fibre Channel and Gigabit Ethernet.

The performance monitoring for SONET/SDH modes includes line and section overhead processing at STS-12/STM-4 (OC12), STS-48/STM-16 (OC48) and STS-192/STM-64 (OC192) rates. In addition 8B/10B processing supports Fibre Channel and Gigabit Ethernet protocols.

The core is configured via a generic CPU interface, allowing the data rate and mode of operation (SONET/SDH or 8B/10B) to be selected. For each mode of operation a set of performance statistics is maintained that is accessible via the CPU interface.

Functional Description

The core receives data from the incoming data stream synchronous to the core system clock. Core operating frequencies up to 155.52MHz combined with flexible input bus widths of 16 and 64 bits provide support for data rates up to 9.953 Gb/s.

A frame pulse input is used to indicate frame boundaries for both SONET/SDH and 8B/10B modes of operation. A word alignment enable output is provided to allow an external pattern matcher to align the data stream to the SONET/SDH frame or 8B/10B K28.5 character. This is asserted whilst the core is seeking frame or character alignment.

When operating in SONET/SDH mode, the core monitors the frame alignment to generate Out of Frame (OOF) and Loss of Frame (LOF) alarms. Once frame alignment has been achieved, the SONET/SDH processor calculates B1 errors and descrambles the data for further processing. This includes, B2 error calculation, M1 octet capture, K1 and K2 octet capture and J0 section trace capture. The K2 octet is used to generate the alarm indication signal (AIS) and the Remote Defect Indicator (RDI). The M1 octet is used to generate the Remote Error Indicator (REI).

When operating in 8B/10B mode, character synchronisation is on a single code word containing the k28.5 character. Once alignment is achieved each 10 bit word is checked to determine if it is a legal 8B/10B code and if the code word violates the 8B/10B disparity rules.

Interface Configuration

Features

• Data rates up to 2.488Gb/s
• OC-48, OC-12, OC-3, GbE, & FC
• CPU Interface
• Suitable for FPGA/ASIC technology

• SONET/SDH Processing
• Loss of Signal Status
• Frame Alignment Status
• B1 Error Count
• B2 Error Count
• AIS Status
• RDI Status
• REI Status
• M1 Octet Capture
• K1/K2 Octet Capture
• J0 Octet Capture

• 8B/10B Processing
• Loss of Signal Status
• Loss of Sync. Count & Status
• Invalid Code Count & Status
• Disparity Error Count & Status

Target Applications

• Performance Monitoring
• Network Analyser

General Description

The 2.5G Multi-Rate PM core provides multi rate performance monitoring for several standard protocols including SONET, SDH, Fibre Channel and Gigabit Ethernet.

The performance monitoring for SONET/SDH modes includes line and section overhead processing at STS-3/STM-1 (OC3), STS-12/STM-4 (OC12) and STS-48/STM-16 (OC48) rates. In addition 8B/10B processing supports Fibre Channel and Gigabit Ethernet protocols.

The core is configured via a generic CPU interface, allowing the data rate and mode of operation (SONET/SDH or 8B/10B) to be selected. For each mode of operation a set of performance statistics is maintained that is accessible via the CPU interface.

Functional Description

The core receives data from the incoming data stream synchronous to the core system clock. Core operating frequencies up to 155.52MHz combined with flexible input bus widths of 4, 8, 10 and 16 bits provide support for data rates up to 2.488 Gb/s.

A frame pulse input is used to indicate frame boundaries for both SONET/SDH and 8B/10B modes of operation. A word alignment enable output is provided to allow an external pattern matcher to align the data stream to the SONET/SDH frame or 8B/10B K28.5 character. This is asserted whilst the core is seeking frame or character alignment.

When operating in SONET/SDH mode, the core monitors the frame alignment to generate Out of Frame (OOF) and Loss of Frame (LOF) alarms. Once frame alignment has been achieved, the SONET/SDH processor calculates B1 errors and descrambles the data for further processing. This includes, B2 error calculation, M1 octet capture, K1 and K2 octet capture and J0 section trace capture. The K2 octet is used to generate the alarm indication signal (AIS) and the Remote Defect Indicator (RDI). The M1 octet is used to generate the Remote Error Indicator (REI).

When operating in 8B/10B mode, character synchronisation is selectable to provide synchronisation on a single code word containing the k28.5 character or synchronisationaccording to the IEEE 802.3 Annex 36. Once alignment is achieved each 10 bit word is checked to determine if it is a legal 8B/10B code and if the code word violates the 8B/10B disparity rules.

Interface Configuration

Features

• Single-cycle A1/A2 search algorithm provides the fastest possible frame alignment time
• Programmable 3, 12, 48 or 64-pair A1/A2 search mask
• Detects SEF, LOF and LOS alarm conditions
• Programmable set and clear thresholds for LOF, LOS and programmable set threshold for SEF
• Aligns incoming data to correct byte and word boundaries
• Row and Column counter outputs provided aligned with output data.
• Short-frame mode for simulation
• Suitable for FPGA and ASIC technology target deployment
• GR-253-CORE, T1.105 and G.707 compliant

Target Applications

• SONET/SDH 40Gb/s network equipment
• SONET/SDH 40Gb/s test equipment

General Description

The SONET/SDH Framer and Data Aligner core provides frame detection and data alignment for OC-768/STM-256. The core performs A1/A2 frame detection from an arbitrary alignment and aligns the data to the correct byte and word boundaries. Row and column counters are generated along with the aligned data to enable the location of any word within the SONET/SDH frame. Severely Errored Frame (SEF), Loss of Frame (LOF) and Loss of Signal (LOS) detection is also performed with programmable thresholds.

The core is fully compliant to Telcordia GR-253-CORE, ANSI T1.105 and ITU-T G.707.

Functional Description

The core receives data via the 256-bit data bus clocked at a nominal 155.52MHz. Incoming OC-768/STM-256 (concatenated or non-concatenated) data is monitored for A1 and A2 bytes. Valid frame declaration is selectable after 3, 12, 48 or 64 A1/A2 pairs.

Once a valid frame has been found, the internal row and column counters are reset and the core re-aligns the incoming data to both byte and word boundaries.

The core waits until the next expected frame boundary, and again checks for valid A1/A2 pairs. If a valid frame is found the SEF alarm is cleared. The core checks for a valid framing pattern during each frame. If frame errors are detected and they exceed the threshold, the SEF alarm is asserted and the core will seek frame alignment.

If the duration of the SEF alarm exceeds the set threshold for the LOF alarm, LOF will be asserted. LOF will remain asserted until SEF is cleared and there are no frame errors for the period specified by the LOF clear threshold.

Incoming data is also monitored for the all zeroes condition. If the duration of this condition exceeds the set threshold for the LOS alarm, LOS will be asserted. The LOS alarm is cleared when two valid frames are detected or the all zeroes condition does not occur for the period specified by the LOS clear threshold.

Interface Configuration

Features

• Single-cycle A1/A2 search algorithm provides the fastest possible frame alignment time
• Programmable 3, 12, 48 or 64-pair A1/A2 search mask
• Detects SEF, LOF and LOS alarm conditions
• Programmable set and clear thresholds for LOF, LOS and programmable set threshold for SEF
• Aligns incoming data to correct byte and word boundaries
• Row and Column counter outputs provided aligned with output data.
• Short-frame mode for simulation
• Suitable for FPGA and ASIC technology target deployment
• GR-253-CORE, T1.105 and G.707 compliant

Target Applications

• SONET/SDH 10Gb/s network equipment
• SONET/SDH 10Gb/s test equipment

General Description

The SONET/SDH Framer and Data Aligner core provides frame detection and data alignment for OC-192/STM-64. The core performs A1/A2 frame detection from an arbitrary alignment and aligns the data to the correct byte and word boundaries. Row and column counters are generated along with the aligned data to enable the location of any word within the SONET/SDH frame. Severely Errored Frame (SEF), Loss of Frame (LOF) and Loss of Signal (LOS) detection is also performed with programmable thresholds.

The core is fully compliant to Telcordia GR-253-CORE, ANSI T1.105 and ITU-T G.707.

Functional Description

The core receives data via the 64-bit data bus clocked at a nominal 155.52MHz. Incoming OC-192/STM-64 (concatenated or non-concatenated) data is monitored for A1 and A2 bytes. Valid frame declaration is selectable after 3, 12, 48 or 64 A1/A2 pairs.

Once a valid frame has been found, the internal row and column counters are reset and the core re-aligns the incoming data to both byte and word boundaries.

The core waits until the next expected frame boundary, and again checks for valid A1/A2 pairs. If a valid frame is found the SEF alarm is cleared. The core checks for a valid framing pattern during each frame. If frame errors are detected and they exceed the threshold, the SEF alarm is asserted and the core will seek frame alignment.

If the duration of the SEF alarm exceeds the set threshold for the LOF alarm, LOF will be asserted. LOF will remain asserted until SEF is cleared and there are no frame errors for the period specified by the LOF clear threshold.

Incoming data is also monitored for the all zeroes condition. If the duration of this condition exceeds the set threshold for the LOS alarm, LOS will be asserted. The LOS alarm is cleared when two valid frames are detected or the all zeroes condition does not occur for the period specified by the LOS clear threshold.

Interface Configuration

Features

• Uses CRC32 Polynomial of x³² + x²⁶ + x²³ + x²² + x¹⁶ + x¹² + x¹¹ + x¹⁰ + x⁸ + x⁷ + x⁵ + x⁴ + x² + x + 1.
• Maximum Clock Speed of 180MHz.
• 256-bit wide Data bus input.
• Start of Packet and End of Packet aligned to any octet boundary.
• Any packet size supported.
• Maximum packet rate of one per clock cycle, or up to 180 million packets per second.
• Targets Xilinx Virtex 2 Pro FPGA technology.
• Resource Utilization is 5500 Slices.
• All incoming signals are replicated at output with identical latency to CRC32 Core function latency to simplify system integration.

Target Applications

• OC-768 Telecommunications Systems.
• Other 40Gb/s Data Processing systems.

General Description

The CRC32 Core consists of a 256-bit wide CRC32 calculator intended for use in OC-768 applications. It uses the standard CRC32 Polynomial of x³² + x²⁶ + x²³ + x²² + x¹⁶ + x¹² + x¹¹ + x¹⁰ + x ⁸ + x⁷ + x⁵ + x⁴ + x² + x + 1.

The CRC32 Core targets a Xilinx Virtex 2 Pro FPGA. In this target technology it may be clocked at up to 180MHz. This clock speed supports data processing at 40Gb/s data rates. Incoming packets may have their first and last octets aligned to any octet boundary on the 256-bit word. All packet sizes are supported, with the restriction that the maximum packet rate is one packet per clock cycle.

All inputs and outputs are synchronous to the CLK input, except the ARST input.

Functional Description

Transmit

In a typical application of a transmit block in a communications system, the CRC32 bus output contains the CRC32 value to append to the packet data leaving the core.  Control signals are reproduced at the outputs, with a delay matching the latency of the CRC32 calculation.  The CRC32 value may be externally shifted and inserted into a 4 octet space trailing the packet.

Receive

In a typical application of a receive block in a communications system, the CRC32 bus output contains the CRC32 value of the processed packet data. This value must be externally compared with the expected CRC32 within the packet. If the comparison is true, then the CRC32 check was correct, otherwise there was an error in the packet data.  The expected CRC32 is not extracted from the packet.

Timing

The CRC32 Core is a pipelined design to achieve high clock speeds. The Core latency is a constant value of 40 clock cycles for the Xilinx Virtex 2 Pro target technology.