PDH

Interface Configuration

Features

• H.110 Bus Compliant
• 32 Streams Supported
• 8.192MHz Stream Rate
• 4,096 Channels per Interface

• Backplane Interface and 2 PTMC Site Interfaces
• Generic Memory Interface
• Constant Latency
• Dual Connection Memory
• Targets Xilinx Spartan FPGA technonlogy for low cost

Target Applications

• CompactPCI H.110 Systems
• Backplane Switches

General Description

The H.110 TDM Switch core provides a fully H.110 compatible TDM switch solution for H.110 TDM bus based systems. Providing a backplane interface and 2 PTMC site interfaces, the core is targetted at E1/T1/J1 data processing appliactions.  Switching is performed at the E1 level, in sets of 32 Timeslots.

A dual-bank Connection Memory enables hitless switching when altering stream mappings.  Additionally, an on-board framer synchronises the incoming frame pulse to prevent loss of Switch synchronisation due to frame pulse jitter.

The Core operates in constant-latency mode, enabling use in N x 64 applications where data is transmitted over multiple timeslots.

Functional Description

The Core provides the ability to route sets of 32 Timeslots, referred to as a Timeslot Group between any two Interfaces.  It is also possible to loopback Timeslot Groups on either PTMC Interface.  The Core always delays data by two frames, regardless of the source and destination routing.  Dual Connection Memories are provided, with a mechanism to perform a transition between them on a frame boundary.

The Core operates at 65.536MHz, derived from an external PLL.  The incoming Backplane Frame Pulse passes through a framer which will reject any jitter present with respect to the 65.536MHz clock input.  The state of the framer may be read via the CPU Interface, it may also be reset at any time.

H.110 Interface

The H.110 Interface operates with an 8.192MHz Clock and an 8KHz Frame Pulse.  32 Streams are provided per Interface, each one carrying 128 channels.  This allows for a total of 4,096 channels per Interface.  The Core acts as a Slave on the Backplane Interface, taking the Backplane Clock and Frame Pulse as inputs for timing purposes.   On the PTMC Interfaces, the Core provides Clock and Frame pulse outputs, which are synchronised to the Backplane Clock and Frame Pulse.

Interface Configuration

Features

• Supports 32 Input and 32 Output streams compliant with ST-BUS protocol
• Switch matrix of 16,384 X 16,384 channels, fully non-blocking
• Stream data rate of 32.768Mb/s
• Switching is unidirectional. Bidirectional switching is supported using two instances of the Core
• Switch may be reconfigured while transferring data
• Core Clock speed of 131.072MHz.
• Targeted to Xilinx Virtex-II / Virtex-II Pro FPGA technology.
• Resource Utilization is 600 Slices and 30 Block RAMs

Target Applications

• CompactPCI H.110 Systems
• Backplane Interfaces

General Description

The TDM Switch Core provides a 16,384 by 16,384 channel non-blocking switch targeting telecommunications applications. Data is organized into 32 streams on the input and 32 streams on the output. Each stream operates at 32.768Mb/s and uses a data format compatible to the ST-BUS protocol. Each stream transports 512 channels, of 64Kb/s bandwidth. Lower stream rates are possible for compatibility with other ST-BUS devices.

Data passing through the switch has a latency of two frames. The timing of the output Frames are locked to the input Frame.

Functional Description

The switching function operates on 64Kb/s channel timeslots, which are written to a Data Memory sequentially. A Connection Memory is configured to control the order in which the timeslots appear on the output of the Data Memory.

Connection Memory

The switch uses a Connection Memory to store the map between the Input stream timeslots and the Output stream timeslots. The Connection Memory is organized as a 16,384 x 14 bit array. The Address format of a location in the Connection Memory represents a source stream and channel number, while the data value in that addressed location represents the destination stream and channel number.

Broadcast switching is supported by mapping a single source channel onto multiple destination channels in the Connection Memory.

This memory may be written to at any time to update the switch configuration of a given channel/stream without affecting the operation of other channels/streams.

Data Memory

Data is written sequentially, with each read access controlled by the Connection Memory.

Memory Interface

The channel mapping is written into the Connection Memory via the Memory Interface, which provides a simplified synchronous interface.

Interface Configuration

Features

• Supports 32 Input and 32 Output streams compliant with ST-BUS protocol
• Bi-directional operation supported
• Switch matrix of 16,384 X 16,384 channels, fully non-blocking
• Stream data rate of 32.768Mb/s
• Switch may be reconfigured while transferring data
• Core Clock speed of 131.072MHz.
• Targetted to Xilinx Virtex-II / Virtex-II Pro FPGA technology.
• Resource Utilization is 1300 Slices and 60 Block RAMs

Target Applications

• Backplane Switches

General Description

The TDM Switch Core provides a bi-directional 16,384 by 16,384 channel non-blocking switch targeted at telecommunications applications. It has 32 input streams and 32 output streams. Each stream operates at 32.768Mb/s and uses a data format compatible to the ST-BUS protocol. Each stream transports 512 channel timeslots, each having 64Kb/s bandwidth. Lower stream rates are possible for compatibility with other ST-BUS devices.

Data passing through the switch has a latency of 2 Frames. The timing of the output Frames are locked to the input Frame.

Functional Description

The switching function operates on 64Kb/s channels, which are written to a Data Memory sequentially. A Connection Memory is configured to control the order in which the 64Kb/s channel timeslots appear on the output of the Data Memory.

Connection Memory

The switch uses a Connection Memory to store the map between the Input streams and the Output streams. The Connection Memory is organized as a 16,384 x 14 bit array. The Address of a location in the Connection Memory corresponds to a source stream and channel number, while the Data value in that addressed location corresponds to the destination stream and channel number.

Broadcast switching is supported by mapping a single source channel onto multiple destination channels in the Connection Memory.

This memory may be written to at any time to update the switch configuration of a given channel/stream without affecting the operation of other channels/streams.

Data Memory

Data is written in sequentially, and each read access is controlled by the Connection Memory.

Memory Interface

The channel mapping is written into the Connection Memory via the Memory Interface, which provides a basic synchronous interface.