Client Area

Calyptech provides complete front-to-back development services for VHDL, Verilog, and C-based High Level Design Languages to offer its clients full 'turnkey' solutions in ASIC and FPGA design to deliver your chip right first time. Services also include FPGA to ASIC conversion, IP Core Design and hardware level Verification.

Within our quality assurance framework our system of processes, coding standards and tools ensure that the generated HDL is consistent, maintainable, reusable and rapidly deployable in the client's context.

Calyptech's range of silicon proven IP Core, jumpstart development, assuring rapid time-to-market, and low risk design execution.

Design Specification

After reviewing the Requirements, a Design Document is produced that outlines the architecture of the proposed solution, with a description of each block’s function.  Resource estimates are produced and system level issues such as the clocking and reset strategy are documented.

In the development of each system block design, consideration is given to the attributes which would help in diagnostics; with probe points brought out to pins, visibility of internal state information and extra controls added to help with functional simulation and the "live" in-system verification of the real silicon.

Design Coding

With expertise in the common hardware description languages including VHDL, Verilog and C, Calyptech can execute your design task. Our coding standards ensure that maintainable code is generated efficiently with due consideration to speed-area optimisation and technology target.

Functional Simulation

At the simulation stage, self-checking testbenches are developed which facilitate automated regression testing. Using code coverage tools provides an objective measure of how completely the code has been simulated. This measure is useful in assessing the thoroughness of the simulation to establish confidence in the quality of the code. It also helps to identify the holes in the simulation coverage.

Logic Synthesis

During coding, the target technology is taken into consideration to ensure a design will require minimal iterations to reach timing closure.  Through understanding the timing characteristics of the technology and the available primitive elements a design can be brought to closure much more rapidly.  Synthesis tool features are used where appropriate to achieve higher productivity, and manual optimization is used where maximum performance is a requirement.

Intellectual Property Cores

Calyptech offer a growing range of IP Cores, as part of the ongoing effort to assist our clients innovate, differentiate and meet their market time windows.

ASIC Verification

Verifying the functionality and timing of an ASIC at the system level is one of the most important aspects of successful design.  The verification task for a complex ASIC can take up to 70% of the overall design effort, and must be an integral part of the design process from the outset.

Calyptech have developed verification strategies and guidelines to help in developing test plans that will guarantee rapid closure and success in your verification effort. Key areas in this strategy include:

• Functional verification at the HDL block level using self-checking testbenches to provide a regression test-suite using HDLs, C, C++, PERL, scripting, PLI environment.
• Verification against algorithms modelled in an appropriate HLL such as C, C++, MATLAB.
• Interface verification including adherence to relevant protocols using Bus Functional Models and Bus Monitors
• Code coverage tools to assure simulation rigour
• Scan, JTAG, BIST, ATPG test structures for verification of manufactured devices.
• Test Vector generation from the Testbenches enable verification of the engineering samples against the Test Suite.
• System Prototyping, including board design and development, FPGA stimulus and analysis machines and interface timing confirmation.
• Driver Software development for testing which may be leveraged for end user deployment as a value-add component

Hardware Verification

Once Engineering Samples of the new part have been manufactured, the final stage of the verification effort is to validate the part on a hardware platform.  Calyptech are able to produce hardware platforms for our FPGA and ASIC designs for customer evaluation of the solution.